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From: jesup@pawl3.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC
Message-ID: <443@imagine.PAWL.RPI.EDU>
Date: 29 Feb 88 09:38:46 GMT
References: <9651@steinmetz.steinmetz.UUCP> <kW8iFty00Vs8EnE0ij@andrew.cmu.edu>
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In article <kW8iFty00Vs8EnE0ij@andrew.cmu.edu> zs01+@andrew.cmu.edu (Zalman Stern) writes:
	    ^^^^  interesting user name

>First, in the "DARPA MIPS core ISA", which binding does "MIPS" take? Is this 
>MIPS the corporation, MIPS the Stanford research project, or MIPS the vacuous 
>abbreviation?

	The vacuous abbrev.

>Could you post the ALU opcodes available? Notably do they include multiply an 
>divide? (I know this is probably a stupid question.)

	Ever seen a multiply or divide as 1 instruction in a RISC?  No, of
course they are not there.  No direct support on CPU for them either.  I will
say more on this issue when the FPU is formally announced.  You can do them
in the CPU in software if you want, takes a few cycles though.

>I don't understand the virtual memory implementation at all. I would 
>appreciate it if someone could elaborate on how this works.

	It's not virtual memory, but memory protection and address translation.
It allows you to declare power-of-2 sized allocations for a task in both
instruction & data memories.  I really don't want to go into the bit-banging
here & now, however.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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