Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!amdahl!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: RISC is a nasty no-no!
Message-ID: <20593@amdcad.AMD.COM>
Date: 29 Feb 88 18:30:53 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP> <284@scdpyr.UUCP> <25699@linus.UUCP>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 25

In article <25699@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes:
| There's something about RISC architectures in general that I find 
| confusing. Since they (read SPARC or equivalent) have no integer multiply
| instructions, any code which has a fair number of these is going to
| be slow.

What makes you think that a single integer multiply instruction would be
faster?  On CISC machines, these are normally expanded to a series of
multiply-step iterations (which most RISC machines have as an
instruction).  Only if you have architectural support for fast
multiplication (i.e. a large multiplier array) is a single multiply
instruction beneficial.

| This would include any program which had access to 2-D arrays
| since one must do multiplications (unless the array sizes are a convenient
| power of 2) to get the array indices right. Any code that accesses a[i][j]
| should run like a pig on such machines.

A multiply by a constant (as in the case of a 2-dimensional array
access in C) is almost always performed faster with an inline series of
shifts and adds than with a multiply.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)