Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!ncr-sd!dennisr From: dennisr@ncr-sd.SanDiego.NCR.COM (Dennis Russell) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC Message-ID: <2065@ncr-sd.SanDiego.NCR.COM> Date: 29 Feb 88 23:09:49 GMT References: <9651@steinmetz.steinmetz.UUCP> <443@imagine.PAWL.RPI.EDU> Reply-To: dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) Organization: NCR Corporation, Rancho Bernardo Lines: 16 Keywords: MIPS R2000, RISC Summary: RISC Multiply/Divide In article <443@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes: > Ever seen a multiply or divide as 1 instruction in a RISC? No, of >course they are not there. No direct support on CPU for them either. I will >say more on this issue when the FPU is formally announced. You can do them >in the CPU in software if you want, takes a few cycles though. > The MIPS R2000 supports 32-bit integer signed and unsigned multiply and divide. Multiply and divide operations are performed by a separate, autonomous execution unit within the R2000. After a multiply or divide operation is started, execution of other instructions may continue in parallel. -- Dennis Russell | NCR Corp., M/S 4720 phone: 619-485-3214 | 16550 W. Bernardo Dr. UUCP: ...{ihnp4|pyramid}!ncr-sd!dennisr | San Diego, CA 92128