Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!hansen
From: hansen@mips.COM (Craig Hansen)
Newsgroups: comp.arch
Subject: Re: RISC is a nasty no-no!
Message-ID: <1721@mips.mips.COM>
Date: 29 Feb 88 23:47:14 GMT
References: <179@wsccs.UUCP> <3530@killer.UUCP> <7507@apple.Apple.Com>
Lines: 43

In article <7507@apple.Apple.Com>, bcase@Apple.COM (Brian Case) writes:
> In article <3530@killer.UUCP> elg@killer.UUCP (Eric Green) writes:
> >I've used a Pyramid 90x and an IBM RT. I've read papers on the AMD29000 and
> >the MIPSco chip. I see no inherent reason for portable programs to not run on
> >any of them, except possibly the 29000 (which lacks byte addressing in its
> >native rendition).
> 
> Wait a minute, I beg to differ with "lacks byte addressing in its native
> rendition."  There are byte and halfword (16-bit) insert and extract
> operations.  These give you everything you need (yes, yes, I know with
> argueable efficiency).  Now, if you meant arbitrary byte *alignment,*
> then yeah, but the 29K isn't unique there.  Note that the Pyramid machines
> are little endian (aren't they?).  This helps non-portable code become
> portable.

Tim says that you can use either the insert and extract operations,
or, in a machine that has external hardware to provide byte addressing
in the memory system itself, you can use direct load and store
byte/halfword operations.  It would seem that if you wished, you could
provide unaligned load and store halfword/word operations with a great
deal of additional external hardware, except that there's no way to
handle items that cross page boundaries. [Not an issue if the MMU isn't
in use, of course.]

In any case, I have two questions:

1) In AMD's performance models, which memory model is used?
	For full clock rate systems, I don't see how you could
	resonably build the direct partial-word addressed machine.
	[The MIPS processors perform the required shifting/extracting
	at full clock rate on the processor chip, and so directly
	handles partial-word operands without additional hardware.]

2) Which memory model does the compiler generate?
	What effect does this lack of architectural specificity
	have on software compatibility? I presume that I can't
	do anything to make code that uses direct partial-word
	addressing work on a machine that has only full-word addressing.

-- 
Craig Hansen
Manager, Architecture Development
MIPS Computer Systems, Inc.
...{ames,decwrl,prls}!mips!hansen or hansen@mips.com   408-991-0234