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From: jesup@pawl19.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: RISC is a nasty no-no!
Message-ID: <450@imagine.PAWL.RPI.EDU>
Date: 1 Mar 88 06:18:29 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP> <284@scdpyr.UUCP> <25699@linus.UUCP>
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In article <25699@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes:
>There's something about RISC architectures in general that I find 
>confusing. Since they (read SPARC or equivalent) have no integer multiply
>instructions, any code which has a fair number of these is going to
>be slow.

	Ever noticed how long a multiply takes on a 68000?  And that's
only a 16x16=32 multiply!  The fact that it takes multiple instructions
to do a multiply doesn't mean it isn't a FAST multiply.  Almost all (or
maybe all) RISC machines have some multiply support in hardware to make
multiplies take a reasonably small amount of time.  The only way to do one
fast (on any chip) is to throw a giant array-multiplier at it, which takes
up an ungodly amount of chip area.  The result is RISC chips have things
like MSTEP instructions, that do 1 or 2 bits of a multiply, so they can
do a multiply in 16 or 32 cycles (approx).  The 68000 requires up to
70+ cycles to do a 16x16 multiply.

>For people who want to use computers to COMPUTE, it appears that SPARC
>is a step in the wrong direction.

	SPARC may not be perfect, and a maxed out 68030 (or maybe even 020)
might be able to beat it on a benchmark or two, but in general it seems
like a win for most applications.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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