Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <1729@winchester.mips.COM>
Date: 1 Mar 88 09:02:00 GMT
References: <1642@mips.mips.COM> <9727@steinmetz.steinmetz.UUCP>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 24

In article <9727@steinmetz.steinmetz.UUCP> sunset!oconnor@steinmetz.UUCP writes:
...
>] A question, though: how would you compare PREFIX to an instruction SHIFT and
>] OR --  SHOR r,lit ::== r := (r<<14)|lit?
>
>PREFIX builds immidiate values that can then be added, ored,
>subtracted or whatever to anything you like. It does not use
>a user register to do this (minor win). And it does NOT access
>the register file, or use the ALU. In a pipelined system
>this is significant : PREFIX as implimented in RPM40 have no latency
>problems (major win). SHOR would have latency problems.

Why would it have latency problems? None of the popular RISCs have
latency problems with r = r op literal for the usual ops.
I.e., any high-performance system is likely to make use of
register-bypassing anyway, so that:
	r = r op literal
	r = r op r
has zero intervening latency (the performance penalty of a
cycle's latency for such things is large).
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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