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From: jesup@pawl3.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <445@imagine.PAWL.RPI.EDU>
Date: 29 Feb 88 09:58:25 GMT
References: <1642@mips.mips.COM> <28200112@ccvaxa>
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Reply-To: beowulf!lunge!jesup@steinmetz.UUCP
Organization: RPI Public Access Workstation Lab - Troy, NY
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In article <28200112@ccvaxa> aglew@ccvaxa.UUCP writes:
>..> Prefix instructions in the GE RPM-40

>A question, though: how would you compare PREFIX to an instruction SHIFT and
>OR --  SHOR r,lit ::== r := (r<<14)|lit? PREFIX always seems to eventually
>require a specification for one of several literal fields it is extending,
>plus it requires state to be saved on interrupts, which leans towards 
>assembling the constant in a register.

	Pipelining!  You can't use the result of an op in the next
instruction!  So you'd have to devote both a register AND intersperse NOPs
between SHORs.  However, on a machine with loopback of ALU results (may
slow things down) it only costs a register, so it doesn't hurt TOO much
(if you have registers to spare, which you very well might not).

	What are these 'several fields' you refer to?  RPM-40 can only have
1 value that might be extended via prefix in any instruction (immediates
for ALU and COND ops, offset for load/store/branch, xp instruction field
for XPINST, etc.)

>    On the other hand, you can always build a decoder that never puts prefix
>into a register at all, but takes prefix and the prefixed instruction as
>one packet. This is nice, and makes it a pity to require the register write.

	RPM-40 does that now, but handles each prefix as it comes along
(there are some hidden resources being used).  What you imply would complicate
the decoder a lot.

>Andy "Krazy" Glew. Gould CSD-Urbana.    1101 E. University, Urbana, IL 61801   

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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