Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!voder!apple!bcase
From: bcase@Apple.COM (Brian Case)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC
Message-ID: <7518@apple.Apple.Com>
Date: 1 Mar 88 18:53:33 GMT
References: <9651@steinmetz.steinmetz.UUCP> <kW8iFty00Vs8EnE0ij@andrew.cmu.edu> <443@imagine.PAWL.RPI.EDU>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Ungermann-Bass Enterprises
Lines: 19

In article <443@imagine.PAWL.RPI.EDU< beowulf!lunge!jesup@steinmetz.UUCP writes:
<In article <kW8iFty00Vs8EnE0ij@andrew.cmu.edu< zs01+@andrew.cmu.edu (Zalman Stern) writes:
<	Ever seen a multiply or divide as 1 instruction in a RISC?  No, of
<course they are not there.  No direct support on CPU for them either.  I will
<say more on this issue when the FPU is formally announced.  You can do them
<in the CPU in software if you want, takes a few cycles though.

Well, I have seen such instructions (they only trap; they were included in
anticipation of on-chip multiply/divide resources).

<<I don't understand the virtual memory implementation at all. I would 
<<appreciate it if someone could elaborate on how this works.
<
<	It's not virtual memory, but memory protection and address translation.
<It allows you to declare power-of-2 sized allocations for a task in both
<instruction & data memories.  I really don't want to go into the bit-banging
<here & now, however.

Isn't the RPM40 scheme just the good-old Stanford MIPS scheme?  Sounds
like it to me.  If so, I can quote some references.