Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!hao!gatech!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <20608@amdcad.AMD.COM>
Date: 1 Mar 88 20:18:25 GMT
References: <1642@mips.mips.COM> <28200112@ccvaxa> <445@imagine.PAWL.RPI.EDU>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 17

In article <445@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes:
| 	Pipelining!  You can't use the result of an op in the next
| instruction!  So you'd have to devote both a register AND intersperse NOPs
| between SHORs.  However, on a machine with loopback of ALU results (may
| slow things down) it only costs a register, so it doesn't hurt TOO much
| (if you have registers to spare, which you very well might not).

Interesting... this is the first RISC processor I have heard of that did
not implement operand {forwarding/bypassing/other names?} around the
ALU.  What prompted the elimination of this feature?  Do you have any
statistics on how many additional nops/stalls are required?

Thanks for any info...


	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)