Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!necntc!linus!bs From: bs@linus.UUCP (Robert D. Silverman) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC Message-ID: <25884@linus.UUCP> Date: 2 Mar 88 13:06:47 GMT References: <9651@steinmetz.steinmetz.UUCP: <443@imagine.PAWL.RPI.EDU> <2065@ncr-sd.SanDiego.NCR.COM> Reply-To: bs@gauss.UUCP (Robert D. Silverman) Organization: The MITRE Corporation, Bedford MA Lines: 34 Keywords: MIPS R2000, RISC In article <2065@ncr-sd.SanDiego.NCR.COM: dennisr@ncr-sd.SanDiego.NCR.COM (0000-Dennis Russell) writes: :In article <443@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes: :> Ever seen a multiply or divide as 1 instruction in a RISC? No, of :>course they are not there. No direct support on CPU for them either. I will :>say more on this issue when the FPU is formally announced. You can do them :>in the CPU in software if you want, takes a few cycles though. :> :The MIPS R2000 supports 32-bit integer signed and unsigned multiply and :divide. Multiply and divide operations are performed by a separate, :autonomous execution unit within the R2000. After a multiply or divide :operation is started, execution of other instructions may continue in :parallel. : : :-- :Dennis Russell | NCR Corp., M/S 4720 :phone: 619-485-3214 | 16550 W. Bernardo Dr. :UUCP: ...{ihnp4|pyramid}!ncr-sd!dennisr | San Diego, CA 92128 RISC architectures are great for some things and uniformly lousy for others. That's all I've been trying to point out. What about 32 x 32 bit multiplies or 64 by 32 bit divides? emul and ediv are marvelous for this. How else would one compute A*B/C A*B mod C where A, B, C are all 32 bit quantities? The result always fits in 32 bits but unless you can compute A*B without overflow you can not get a correct answer to these computations. Bob Silverman