Path: utzoo!mnetor!uunet!steinmetz!ge-dab!codas!pdn!alan From: alan@pdn.UUCP (Alan Lovejoy) Newsgroups: comp.arch Subject: Re: RISC is a nasty no-no! Message-ID: <2378@pdn.UUCP> Date: 2 Mar 88 16:15:56 GMT References: <179@wsccs.UUCP: <696@nuchat.UUCP> <284@scdpyr.UUCP> <25699@linus.UUCP> Reply-To: alan@pdn.UUCP (0000-Alan Lovejoy) Organization: Paradyne Corporation, Largo, Florida Lines: 44 In article <25699@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes: >There's something about RISC architectures in general that I find >confusing. Since they (read SPARC or equivalent) have no integer multiply >instructions, any code which has a fair number of these is going to >be slow. This would include any program which had access to 2-D arrays >since one must do multiplications (unless the array sizes are a convenient >power of 2) to get the array indices right. Any code that accesses a[i][j] >should run like a pig on such machines. I've seen some benchmarks that >suggest SUN-4's are in fact slower than SUN-3's on programs that do a >large amount of integer multiplies/divides. What good is a computer that >can't multiply? Given VAR a: ARRAY RowIndex OF ARRAY ColumnIndex OF Element; If the compiler's code generator (or the assembly hack) stores the ADDRESS of each row at a[row], so that a[row][column] is actually a[row]^[column] (but the rows are stored on the stack, not the heap), then a[row][column] not only does not require multiplication, but will be FASTER than multiplication. Of course, a[MIN(RowIndex)..MAX(RowIndex)] would need to be initialized (possibly using multiplication) once each time the block in which "a" is declared is entered. This scheme takes more memory. Good, fast, cheap: choose any two. On the other hand, fine-tuning a computer architecture so that it gets the best possible performance executing "average" code is guaranteed to result in poor performance in some cases when executing decidedly unaverage code. The question is, to what degree should an architecture cater to pathological cases at the expense of normal ones (or vice versa)? The answer, of course, depends on who will use the architecture to do what. And people won't agree on the answer, which is why there are so many different computer architectures in the world. Which brings me to my main point: don't judge RISC on the characteristics of SPARC. There are other ways to skin a cat, and other cats to skin. Some RISCs do have hardware multiply. --alan@pdn