Path: utzoo!mnetor!uunet!husc6!bbn!gatech!hubcap!Donald.Lindsay
From: Donald.Lindsay@K.GP.CS.CMU.EDU
Newsgroups: comp.hypercube
Subject: RE: bandwidth balance
Message-ID: <999@hubcap.UUCP>
Date: 22 Feb 88 13:11:52 GMT
Sender: fpst@hubcap.UUCP
Lines: 26
Approved: hypercube@hubcap.clemson.edu

I originally said:
>Of course, a Cray isn't simple. I don't have data on the Y-MP, so let us
>assume 8 CPUs, each quad-ported to (some) memory, with 64-bit data paths.
>That gives a 2K-bit-wide data path, versus the 16K on the NCUBE. However, we
>are measuring the Cray, not at the RAM chips, but at a pipelined interface.
>Assuming for simplicity that this gives the Cray an 8:1 speedup, then the
>Y-MP and the NCUBE have similar aggregate potential memory bandwidths.

Steve Reinhardt reports the clock rate of the Y-MP interface as 166.7 MHz.
The NCUBE uses a 10MHz clock, hence the ratio is 17:1, not 8:1. Worse,
the NCUBE can't cycle memory in one clock, and therefore is slowed by
another factor of 2 or 3.

The Y-MP is therefore ahead by perhaps a factor of six. The MFLOPS ratio
would typically be higher, as is the price ratio. As previously pointed
out, all of these have serious caveats.

IBM's proposed TF-1 will have

    32K CPUs * 50 MHz * ( 32 + 64 ) bit-wide-path = 160,000 Gb/s 

i.e. 462 times more than the Y-MP. I firmly believe that IBM can achieve
this (or some significant fraction of it). I am, however, a bit dubious
about the ease with which they expect to get them synchronized (!) and
communicating. Also, the reliability of 3.5MW of CMOS ( and 2048 disks ) is
certainly quite the topic.