Xref: utzoo comp.sys.dec:528 comp.arch:3452
Path: utzoo!utgpu!water!watmath!clyde!rutgers!ames!pasteur!ucbvax!hplabs!nsc!curry
From: curry@nsc.nsc.com (Ray Curry)
Newsgroups: comp.sys.dec,comp.arch
Subject: Re: 8036 counter/timer chip
Keywords: DEC, KXJ11-CA, KXT11-CA, frequency data
Message-ID: <4978@nsc.nsc.com>
Date: 20 Feb 88 21:12:28 GMT
References: <157@pwa-b.UUCP>
Reply-To: curry@nsc.UUCP (Ray Curry)
Organization: National Semiconductor, Sunnyvale
Lines: 22

In article <157@pwa-b.UUCP> anneser@pwa-b.UUCP (Dean Anneser) writes:
>Help !  Has anyone out in netland had experience with the 8036 counter/timer
>
>The problem
>I'm seeing, is that counter_timer_2 is not decremented with the FIRST
>transition through zero, of counter_timer_1.  As the input signal's frequency
>decreases, and counter_timer_1 makes an additional transition through zero,
>counter_timer_2, then will decrement (what appears to be) correctly, but its
>value is one greater than it should be.
>

If I can remember back that far, there are some programming problems with
the CIO mostly with the manner of programming the link.  This may be related 
to the problem you see and I will have to spend a couple of hours with the
manual to try to remember the exact problem.  As I remember off the top of 
my head, care must be taken in programming the registers and setting the 
link.  As a rule of thumb, only handle one flag at a time and the last two
steps are to link the two and enable the count.  

Like I say, I can't remember all of the recommended proceedures.  If I can
remember more, I will let you know.  I may be able to get a hold of the
original designer of the chip.