Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!lll-tis!ames!ptsfa!ihnp4!att-cb!mandrill!howarth
From: howarth@mandrill.CWRU.Edu (David J. Howarth)
Newsgroups: comp.sys.mac
Subject: Mac DMA
Message-ID: <2365@mandrill.CWRU.Edu>
Date: 18 Feb 88 20:50:46 GMT
Reply-To: howarth@mandrill.UUCP (David J. Howarth)
Organization: Case Western Reserve University
Lines: 31
Keywords: DMA Mac

DMA on the Mac, if done correctly, could actually be very advantageous.
The problem with having the CPU handle all the block memory transfers
is that it has to fetch instructions, read from memory/device, write
to memory/device and handle looping. 

  move (An)+,(An)+  takes 9 clock cycles best case on the Mac II
                         12 clock cycles worst case
  DBcc Dn,<label>  takes 3 clock cycles best case, count not expired
                         11 clock cycles worst
    
  So the 68020 needs from 12-23 cycles per 32 bit word for block 
  memory moves.  When it is driving the SCSI chip, it can move
  only a byte at a time, which means that it would take 4 one byte
  transfers to move 32 bits, or 48-92 cycles per 32 bit word when
  doing SCSI transfers.
  A good DMA controller, on the other hand, can pump data into 
  memory at 4 clock cycles per 32 bit word (after setup) if designed
  correctly.  Even if the processor can not access RAM while the DMA
  controller is, the performance difference is still substantial.
  These times were acquired from the 68020 user's manual from
  Motorola and assume a 1 clock cycle wait state which the
  Mac II uses.
  One thing to keep in mind, though, is that even a factor of
  10 increase in performance at this low level will NOT result
  in a user perceivable speedup of 10.  It will be faster from
  the user's standpoint, but by how much is not easily quantified.

           Give me DMA or give me death :-) :-)
-- 
usenet: {decvax, cbosgd, sun}!mandrill!howarth    David J. Howarth
csnet:  howarth@mandrill.CWRU.edu
arpa:   howarth@mandrill.CWRU.edu