Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!hao!gatech!bloom-beacon!mit-eddie!apollo!nelson_p@apollo.uucp
From: nelson_p@apollo.uucp
Newsgroups: sci.electronics
Subject: Electronic Time Capsule
Message-ID: <3a7af473.44e6@apollo.uucp>
Date: 24 Feb 88 19:39:00 GMT
Sender: user@apollo.uucp
Lines: 52
To: sci.electronics@news




 In response to my proposal for an electronic time capsule,
 John Nagle observes:

>      Timing is the easy part.  It's not at all clear that we have the
>technology to make electronics with a shelf life of a century, let alone
>an operating life that long.
>
>      Capacitive-type EPROMS will probably discharge within a decade or
>two.  Lifetimes of other components are more problematical.  Ceramic-packaged
>militarized ICs might make it.  Electrolytic capacitors probably wouldn't.
>
>      A good first step would be to build something that would survive
>a year of 2-hour freeze/bake cycling.
>
>      Whatever it is, it should have redundancy.  It would be useful to
>have two units checking each other, and as soon as one failed, the 
>other would go on the air, so it would make itself known rather than
>being forgotten.



  Of course, everything would be MIL-SPEC and I've tried to
  keep the design simple to promote reliability.  I've been
  quite amused by some of the proposals for wind generators,
  atomic power, microcomputers with EAROM, etc.  These people
  have never heard the KISS rule and I doubt that such designs
  would last a decade.  Another advantage of keeping it simple
  is low cost.  If it's cheap then I can make a dozen or more
  and that way increase the odds that at least a few might last
  a century or two.
 
  My prototype has 6 CMOS IC's, all SSI and MSI and one transistor
  (for the transmitter).   It transmits a short message in CW
  with a power of a couple hundred milliwatts.  Of course, in
  centuries to come nobody will probably use CW so I should change
  that (to what?).   I assume that because of the larger chip
  geometry features relative to LSI or VLSI devices, SSI and
  MSI devices should be more reliable.  But I admit that I don't
  know what the long-term failure modes for CMOS logic are.  If
  it's contamination from the air then perhaps I can seal the
  board or individual devices.  If it's the result of micro-
  fracturing due to constant temperature cycling then maybe
  using an enclosure with a large thermal mass will reduce
  the *rate* of temperature change to reduce thermal shock.
  I don't know.

  What did you mean, 'timing is the easy part'?  To me that
  is still the biggest unsolved part of the problem. 

                                            --Peter Nelson