Path: utzoo!mnetor!uunet!amdahl!nsc!voder!apple!baum
From: baum@apple.UUCP (Allen J. Baum)
Newsgroups: comp.arch
Subject: RPM40 questions
Message-ID: <7484@apple.UUCP>
Date: 3 Mar 88 00:35:03 GMT
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 18

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I am puzzled by some things in the RPM-40 instruction set encoding. The ISSCC
arcticle showed the opcode formats, including the load/store format, which
looks like:  2    1     1   4    4    4
            op   ld/st  s  dst base offset

Now, I thought I was told that the 's' bit was for doing signed ld/st, but
a signed store makes no sense. I also thought that I was told that the
load/store ops were word/halfword/byte, but the encoding doesn't mention them,
and load word signed makes no sense, either. So, GE guys, whats the story?

Also the XPLD (which I assume is eXternal Processor LoaD) doesn't store.

Finally, could someone explain in just a little more detail what the memory
protection scheme is?  Thanks a lot.

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