Path: utzoo!mnetor!uunet!steinmetz!sungoddess!oconnor
From: oconnor@sungoddess.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <9764@steinmetz.steinmetz.UUCP>
Date: 3 Mar 88 04:22:14 GMT
References: <445@imagine.PAWL.RPI.EDU>
Sender: news@steinmetz.steinmetz.UUCP
Reply-To: oconnor%sungod@steinmetz.UUCP
Organization: GE Corporate R&D Center
Lines: 21

An article by tim@amdcad.UUCP (Tim Olson) says:
] In article <445@imagine.PAWL.RPI.EDU> beowulf!lunge!jesup@steinmetz.UUCP writes:
] Interesting... this is the first RISC processor I have heard of that did
] not implement operand {forwarding/bypassing/other names?} around the
] ALU.  What prompted the elimination of this feature?  Do you have any
] statistics on how many additional nops/stalls are required?
] 
] Thanks for any info...
] 	-- Tim Olson

Well, CRAYs are KINDA "RISC"y, and they don't loop results directly back :-)

But seriously, this will be one of the things that the RPM40 team hope
to present in a paper submitted to ICCD, if it gets accepted. Until
then, our DARPA contract prohibits disclosure. It could be worse,
at least it's not ITARS restricted. But believe me, it was NOT
a decision we made likely. OR neccesarily correctly :-)
--
    Dennis O'Connor			      oconnor%sungod@steinmetz.UUCP
		   ARPA: OCONNORDM@ge-crd.arpa
   (-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)