Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ptsfa!pacbell!att-ih!ihnp4!inuxc!iuvax!pur-ee!uiucdcs!uxc.cso.uiuc.edu!ccvaxa!aglew
From: aglew@ccvaxa.UUCP
Newsgroups: comp.arch
Subject: Re: Cray 2 has 2GW address
Message-ID: <28200117@ccvaxa>
Date: 1 Mar 88 16:31:00 GMT
References: <235@amelia.nas.nasa.gov>
Lines: 15
Nf-ID: #R:amelia.nas.nasa.gov:235:ccvaxa:28200117:000:804
Nf-From: ccvaxa.UUCP!aglew    Mar  1 10:31:00 1988


> ...although I wonder if processes that do not use the vector registers 
> do, in fact, flush them...

Gould NP has a VRIU (Vector Register IN Use) bit that is set whenever a
vector register is written to. So processes that do not use the vector
registers do not have to have them flushed (although for security they 
are cleared). Ditto, interrupt handlers do not have to save/restore
the vector registers unless they were in use, and the ISR wants to use them
for something like high speed copies. Moreover, this can apply to a
process that uses vectors in some phases, but not others.
    I imagine other vector machines have similar mechanisms. Can anybody
describe them for us?

While I'm at it, it occurs to me that another flag to cause a trap if a
vector register is read might have advantages.