Path: utzoo!mnetor!uunet!husc6!linus!alliant!lackey
From: lackey@Alliant.COM (Stan Lackey)
Newsgroups: comp.arch
Subject: Was: RISC is a nasty no-no! More to the point: Supercomputer addresses
Message-ID: <1334@alliant.Alliant.COM>
Date: 3 Mar 88 17:22:23 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP: <284@scdpyr.UUCP> <25699@linus.UUCP> <11199@duke.cs.duke.edu> <25723@linus.UUCP> <8332@eddie.MIT.EDU> <7482@apple.UUCP> <7514@boring.cwi.nl> <17415@think.UUCP>
Reply-To: lackey@alliant.UUCP (Stan Lackey)
Organization: Alliant Computer Systems, Littleton, MA
Lines: 16

In article <17415@think.UUCP> barmar@fafnir.think.com.UUCP (Barry Margolin) writes:
>>...when you start programming on supers you will soon
>>learn that power of two array sizes are the worse choice you can make.
>Could you explain why this is so?

Many supercomputers, and mini-supercomputers, to increase memory bandwidth,
set up independent banks of slow memory and interleave them on low address
bits.  Vector references effectively cause several banks to access/cycle
at roughly the same time, to stream elements to the CPU(s) at very high
rates.

So. Suppose the memory is 8-way interleaved, and the array is a power
of 2 greater than or equal to 8.  All references will go to the same bank,
reducing bandwidth to the CYCLE time of the memory RAM.  DRAM cycle times
are typically 200nS, so you can see what that can do to performance.
-Stan