Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ptsfa!pacbell!att-ih!ihnp4!ho95e!wcs From: wcs@ho95e.ATT.COM (Bill.Stewart.) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; dat Message-ID: <2032@ho95e.ATT.COM> Date: 4 Mar 88 05:22:39 GMT References: <1642@mips.mips.COM> <28200116@ccvaxa> Reply-To: wcs@ho95e.UUCP (46323-Bill.Stewart.,2G218,x0705,) Organization: AT&T Bell Labs 46133, Holmdel, NJ Lines: 26 In article <28200116@ccvaxa> aglew@ccvaxa.UUCP writes: : :> Ever seen a multiply or divide as 1 instruction in a RISC? No, of :>course they are not there. No direct support on CPU for them either. I will :>say more on this issue when the FPU is formally announced. You can do them :>in the CPU in software if you want, takes a few cycles though. : :If your customers spend time doing multiplies or divides, then your RISC :designer will put them in. Cray is the only "RISCy" machine that is widely :known with multiply that springs to mind, though. Same for floating point. The AT&T Digital Signal Processor chips are RISCy, and do single-instruction multiplies, because that's what the chips' customers do. The DSP-32 does 32-bit floating point - each cycle does an add and a multiply if you want them, and/or 16-bit integer ops; I think the pipeline is 4 deep for multiplies. The original chip did 4 Million cycles/sec (16MHz clock?); the current version does 6 Million. The next generation will be faster. The current chip also includes serial and parallel I/O hardware, but only 64K address space; the next will be more general. The DSP-16 does 16-bit integers (multiplies into 36 bits); it's got very limited memory (1-4K on chip), and has a more limited instruction set, but the 16 - 19 million cycles/sec do a multiply and/or add as well as separate integer ops for address calculation. -- # Thanks; # Bill Stewart, AT&T Bell Labs 2G218, Holmdel NJ 1-201-949-0705 ihnp4!ho95c!wcs