Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!eos!eugene
From: eugene@eos.UUCP (Eugene Miya)
Newsgroups: comp.arch
Subject: Re: Was: RISC is a nasty no-no! More to the point: Supercomputer addresses
Message-ID: <254@eos.UUCP>
Date: 4 Mar 88 17:31:11 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP: <284@scdpyr.UUCP> <25699@linus.UUCP> <11199@duke.cs.duke.edu> <25723@linus.UUCP> <8332@eddie.MIT.EDU> <7482@apple.UUCP> <7514@boring.cwi.nl> <17415@think.UUCP> <1334@alliant.Alliant.COM>
Reply-To: eugene@eos.UUCP (Eugene Miya)
Organization: NASA Ames Research Center, Calif.
Lines: 18

In article <1334@alliant.Alliant.COM> lackey@alliant.UUCP (Stan Lackey) writes:
>Many supercomputers, and mini-supercomputers, to increase memory bandwidth,
>set up independent banks of slow memory and interleave them on low address

Actually, I would not say "many."  Crays are the only machines
I have recorded which measureably have this as a problem.  These
machines are no slouches on speed.  They are 'relatively' slow ;-).
Other machines (and I've not run this particular test on the Alliant
because it has a relatively low-resolution clock) have noted
this problem and have made other architectural compromises (e.g., Cyber 205
and IBM 3090 which work around this in different ways),
but maybe I'll get some time and stress (torture) our Alliant ;-).

From the Rock of Ages Home for Retired Hackers:

--eugene miya, NASA Ames Research Center, eugene@ames-aurora.ARPA
  "You trust the `reply' command with all those different mailers out there?"
  "Send mail, avoid follow-ups.  If enough, I'll summarize."
  {uunet,hplabs,hao,ihnp4,decwrl,allegra,tektronix}!ames!aurora!eugene