Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!hplabs!otter!kers
From: kers@otter.hple.hp.com (Christopher Dollin)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; data from ISSCC
Message-ID: <780007@otter.hple.hp.com>
Date: 4 Mar 88 08:47:52 GMT
References: <1642@mips.mips.COM>
Organization: Hewlett-Packard Laboratories, Bristol, UK.
Lines: 16

Version 2 of the Acorn Risc Machine has two multiply instructions (one with,
one without, accumulate), but no divide instruction.

At a seminar I attended, the designer* said that (a) they could fit it on the
chip, and (b) it afforded enough performance increase to be an acceptable
overhead (rather than having a multiply-step, or doing it with shift-and-add).

Mildly surprising, considering the shiftable-register-source in the data
manipulation instructions (gives you multiplies by constants of the form 2^n,
2^(n+1), 2^(n-1) in one instruction). Could it be something to do with having
interpreted BBC Basic as a principal language, so there isn't a compiler to
notice that E*K can be done speedily?

Regards,
Kers.

* well, one of the designers.