Path: utzoo!mnetor!uunet!steinmetz!sungoddess!oconnor
From: oconnor@sungoddess.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <9800@steinmetz.steinmetz.UUCP>
Date: 5 Mar 88 03:39:48 GMT
References: <9758@steinmetz.steinmetz.UUCP>
Sender: news@steinmetz.steinmetz.UUCP
Reply-To: oconnor%sungod@steinmetz.UUCP
Organization: GE Corporate R&D Center
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An article by bcase@apple.UUCP (Brian Case) says:
] In article <9758@steinmetz.steinmetz.UUCP> sungoddess!oconnor@steinmetz.UUCP writes:
] >IMHO, a pipelined processor should run as fast as the its ALU 
] >lets it. Some RISC processors DO NOT do this. Instead, they
] >perform either the operand-read or the result-write for an
] >instruction in the same pipestage as the ALU op.
] 
] Er, which ones do this?  I don't know of any among MIPS, SPARC, Am29000,
] ARM (but it does have a shifter in there, which could be bad), even
] CLIPPER.  In fact, I do know of one, but no one else out there probably
] does (it's still vaporware).

You may be right, I could be wrong. In fact, I think I was. Sorry..

] I still agree that the ALU should govern cycle time (but I would always
] include bypassing; in my experience, there just isn't enough stuff to move
] around to spearate the computations from the uses with useful work a
] significant fraction of the time), but I now know that a much more
] probable cycle time determiner is cache cycle time.  This can be either
] the instruction cache, or the TLB, or whatever.  I suspect that omitting
] bypassing is a bad choice, but like you say, there isn't much "proof."

Smaller caches, like the RPM40 TIB cache, are faster. And can
be just as effective. But I'm not sure the details of the TIB
have been released. I'll expand on it if it has been. What happened
with RPM40 was : whenever anything was too slow to make 40MHz,
additional design effort was thrown at it until it was fast enough.
This means we have several near-critical paths. This would have been
impossible without a good process model and simulation tools, of course.
Did I ever mention that the ALU was laid out about a half-dozen times
so it would make speed ? 
--
    Dennis O'Connor			      oconnor%sungod@steinmetz.UUCP
		   ARPA: OCONNORDM@ge-crd.arpa
   (-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)