Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!umd5!uvaarpa!mcnc!duke!dfk
From: dfk@duke.cs.duke.edu (David Kotz)
Newsgroups: comp.arch
Subject: Re: Was: RISC is a nasty no-no! More to the point: Supercomputer addresses
Message-ID: <11233@duke.cs.duke.edu>
Date: 5 Mar 88 01:54:55 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP: <284@scdpyr.UUCP> <1334@alliant.Alliant.COM>
Organization: Duke University CS Dept.; Durham, NC
Lines: 22
Summary: for column access, yes


In article <1334@alliant.Alliant.COM>, lackey@Alliant.COM (Stan Lackey) writes:
> 
> So. Suppose the memory is 8-way interleaved, and the array is a power
> of 2 greater than or equal to 8.  All references will go to the same bank,
> reducing bandwidth to the CYCLE time of the memory RAM.  DRAM cycle times
> are typically 200nS, so you can see what that can do to performance.
> -Stan

This is true if your array is stored in row-major order (i.e. elements
of a row spread across modules, elements of a column all in one
module), and you are trying to access a given column. If you are
accessing successive elements of a row it doesn't matter what the
dimension of your array is. A good discussion of all this can be found
in Stone, "High Performance Computer Architectures", Addison Wesley
1987, chapter 5, section 3. 

David Kotz
-- 
Deparment of Computer Science, Duke University, Durham, NC 27706
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