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From: jesup@pawl23.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: Longer quote, RPM-40 performance
Message-ID: <477@imagine.PAWL.RPI.EDU>
Date: 5 Mar 88 08:28:52 GMT
References: <9689@steinmetz.steinmetz.UUCP> <9732@steinmetz.steinmetz.UUCP> <1731@winchester.mips.COM>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: beowulf!lunge!jesup@steinmetz.UUCP
Organization: RPI Public Access Workstation Lab - Troy, NY
Lines: 47
Keywords: DAIS, 14 MIPS, General Electric

In article <1731@winchester.mips.COM> mash@winchester.UUCP (John Mashey) writes:
>But, if people want to claim that it's a good UNIX engine,
>it would be nice to know:
>	a) How you use the MMU to do a modern UNIX?
>	b) How you turn the SRAM into a cache, because NOBODY cares about
>	a workstation whose memory is limited to the size of SRAM you
>	can drive off the CPU? (and what the performance hit is?)
>	c) How much of a performance hit one takes from the various
>	design choices when trying to use it in the general environment?

	I think the answer to most of these questions would be an external
cache/mmu chip(s).  I really wish I could say more about this, let it stand
that these considerations were most definitely part of the overall system
design, and more than a bit of research was done to find the answers.

>Just out of curiosity, is the RPM intended for ADA, or C, ... or assembler?

	Well, I's bet on Ada, and maybe C or pascal.  In fact, the whole
Core ISA idea was to have compilers that generate Core, and then use each
processors backend software to translate it into native assem and reorganize
it.
	One reason for the lack of lots of benchmarks:  no really good
Core ISA compilers.  I'm not sure about the present, but when I was working
on it we had the MIPS pascal compiler (yes, MIPS Inc was involved in the
Core ISA project).  They added a Mips->Core translator, which produced
pretty poor (and often wrong/illegal) Core ISA.  RISC compilers are supposed
to be GOOD optimizing compilers, so any numbers from the pascal compiler
would be skewed.  This isn't to impune the compiler per se, but mainly
the translator.
	Remember this is a mutli-company government research project, not
an attempt to take over the micro-RISC world, so GE hasn't thrown dozens
of programers at compilers/utilities/benchmarks the way CPU-sellers do.
Hopefully by now there are some good compilers, but I wouldn't know, as I
no longer am consulting there.

>-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>

I think these issues have been beaten to death.  Anyone want a new subject,
like reorganizing algorithms? (my specialty :-)  Is there anyone else out
there that does linking before reorganization?  Or given thought to doing
optimal (instead of near-optimal) reorganization in small code blocks?

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
  \/    (uunet!steinmetz!beowulf!lunge!jesup) BIX: rjesup

(-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)