Path: utzoo!mnetor!uunet!husc6!tut.cis.ohio-state.edu!bloom-beacon!athena.mit.edu!wesommer
From: wesommer@athena.mit.edu (William E. Sommerfeld)
Newsgroups: comp.arch
Subject: Re: RISC processor in new Apollo system
Message-ID: <3504@bloom-beacon.MIT.EDU>
Date: 5 Mar 88 18:30:51 GMT
References: <2742@druhi.ATT.COM>
Sender: daemon@bloom-beacon.MIT.EDU
Reply-To: wesommer@athena.mit.edu (William E. Sommerfeld)
Distribution: comp
Organization: Massachusetts Institute of Technology
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In article <2742@druhi.ATT.COM> pjt@druhi.ATT.COM (TaysomPJ) writes:
>I'm curious as to which RISC processor the new Apollo system is using.
>In the trade rags, they are claiming 15 MIPS and 8 MFLOPS.
>If anyone has any non-proprietary information, I'ld be interested in
>receiving electronic or regular mail.  Thanks.

Disclaimer: the following information is my recollection of a
conversation I had this week; I have not seen this information
published anywhere, nor have I seen any references in the trade rags
to this system.

The information I heard from some Apollo _software_ types I was
talking with earlier this week was more like 25 `MIPS' (but more like
36M actual instructions/sec) and 25 `MFLOPS' (the latter is probably
the infamous `peak' number); the FP unit consists of an adder and a
multiplier; apparantly, with an 8(?) stage pipeline in the FP unit (as
compared to a three (?) stage pipeline in the integer unit), they can
do one FP `operation'/cycle.  Also, he mentioned the use of a
CDC-style `scoreboard' to handle pipeline conflicts---this was done in
hardware, rather than software, so they're free to rearrange things in
new implementations without needing to adjust the compiler to
compensate; of course, to get really optimal code for the new
implementations, they still have to tweak the compiler anyway.  The
emphasis was on `balanced' floating point and integer computation.

This is supposedly used in an (up to) four processor tightly coupled
multiprocessor which is supposedly a `100 MIPS' machine.

					- Bill