Path: utzoo!mnetor!uunet!steinmetz!sungoddess!oconnor
From: oconnor@sungoddess.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: 16 & 32 bit vs 32 bit only instructions for RISC.
Message-ID: <9801@steinmetz.steinmetz.UUCP>
Date: 6 Mar 88 01:18:26 GMT
References: <7538@apple.Apple.Com>
Sender: news@steinmetz.steinmetz.UUCP
Reply-To: oconnor%sungod@steinmetz.UUCP
Organization: GE Corporate R&D Center
Lines: 19

An article by beowulf!lunge!jesup@steinmetz.UUCP says:
] 	Pads aren't the limiting factor, but PINS (and bandwidth) are.
] The RPM-40 has 144 'pins' (not PGA, but leadless chip carrier), which was the
] biggest certifed package we could find.  We would KILL for more pins!
] (Of course, by now there are probably larger certified packages.)
] 
]      //	Randell Jesup		      Lunge Software Development

Sorry, Randell, not quite right. The RPM40 CPU and FPU are packaged
in ** 132-pin ** leadless ceramic chip carriers, both for speed and so
that they could eventually be put in 132-pin surface-mount packages.

The impression of PGAs we had back in design time was that they were
slow, huge and NOT compatable with surface mounting. You wouldn't
want to put one in your space-born BM/CCC processor, we thought.
--
    Dennis O'Connor			      oconnor%sungod@steinmetz.UUCP
		   ARPA: OCONNORDM@ge-crd.arpa
   (-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)