Path: utzoo!mnetor!uunet!husc6!yale!lisper
From: lisper@yale.UUCP (Bjorn Lisper)
Newsgroups: comp.arch
Subject: Re: Was: RISC is a nasty no-no! More to the point: Supercomputer addresses
Message-ID: <24605@yale-celray.yale.UUCP>
Date: 6 Mar 88 02:12:10 GMT
References: <179@wsccs.UUCP: <696@nuchat.UUCP: <284@scdpyr.UUCP> <1334@alliant.Alliant.COM> <11233@duke.cs.duke.edu>
Reply-To: lisper@yale-celray.UUCP (Bjorn Lisper)
Organization: Yale University Computer Science Dept, New Haven CT
Lines: 22

In article <11233@duke.cs.duke.edu> dfk@duke.cs.duke.edu (David Kotz) writes:
>In article <1334@alliant.Alliant.COM>, lackey@Alliant.COM (Stan Lackey)
>writes:
>> So. Suppose the memory is 8-way interleaved, and the array is a power
>> of 2 greater than or equal to 8.  All references will go to the same bank,
....
>This is true if your array is stored in row-major order (i.e. elements
>of a row spread across modules, elements of a column all in one
>module), and you are trying to access a given column. If you are
>accessing successive elements of a row it doesn't matter what the
>dimension of your array is.

It seems that a smart compiler should be able to detect certain cases where
array elements are accessed in a order that cause slowdown due to memory
bank conflicts, and change the order of storage to speedup the access. Or
perhaps simply use a hash function to randomize the access pattern? This
is of course not possible in a language like FORTRAN where the order of
storage is strictly specified.

Does anyone have any comments on this?

Bjorn Lisper