Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!voder!apple!bcase From: bcase@Apple.COM (Brian Case) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; dat Message-ID: <7579@apple.Apple.Com> Date: 7 Mar 88 19:49:49 GMT References: <9758@steinmetz.steinmetz.UUCP> <9792@steinmetz.steinmetz.UUCP> Reply-To: bcase@apple.UUCP (Brian Case) Organization: Ungermann-Bass Enterprises Lines: 95 In article <9792@steinmetz.steinmetz.UUCP> oconnor%sungod@steinmetz.UUCP writes: >An article by bcase@apple.UUCP (Brian Case) says: >] In article <9758@steinmetz.steinmetz.UUCP> sungoddess!oconnor@steinmetz.UUCP writes: >] >"Popular RISCs" don't have any latency on >] >ALU ops because they ARE ( No Dennis don't say it, no, no ... ) >] >SLOW SLOW SLOW ! (ARRGGHH he said it ! BAD DENNIS, BAD ) >] >] Boy, I must say I don't know what you are thinking. Do you mean they are >] slow because they don't have 40 MHz versions? Or do you mean that they >] are slow in terms of VAX-equivalent MIPS? > >At least the former, and perhaps the latter, but I obviosly mainly >MEANT it HUMOUROUSLY. Couldn't you tell. No, really, I have to say I couldn't tell. You have to remember that some of us are judging your statements now by the standard that was set a while ago; I didn't save a copy of those early postings, but I do remember you (or someone there) saying things like: "Just wait until ISSCC, then you'll see how to do it right." I can say that I am not the only one who took offense at this and other remarks of yours (or someone there). Those postings don't make you a bad person and they don't make the RPM40 a bad chip, BUT, they did set a rather bad tone and put the burden of proof on you. As for my comments about who has 40 MHz in what quantity in what temperature range, you are right: there was no verifiable substance in my remarks (you, justifiably, used the word "hogwash"). I certainly didn't mean to imply any "willy-nilliness" of design on the part of GE. I shouldn't have said what I said. I probably shouldn't have said anything here. The RPM40 is a great achievment, no one is saying otherwise. My complaints about the RPM40 are architectural: having 16-bit instructions may be a slight advantage now, but I predict it will come back to haunt. In my opinion, and according to the information I have gotten from postings here and a friend who attended the ISSCC, I have seen little to convince me that the RPM40 is showing us how to do it right, in the architectural sense. That, in a nutshell, is my beef. Running UNIX or dhrystone quickly is not the main issue; this is a forum concerned with architectural issues. Of course, architecture can influence how fast dhrystone is run, and implementation can often mean more than anything else. I honestly think the absolute best thing you could do right now is to post a bullet-list of "features" of your machine. This will put an end to questions like "well, how much do you really know about the RPM40?" >The RPM40 runs 40MIPS, all the time, all instructions (even NOPS :-), With the memory system you assume, the Am29000 and I guess the R2000 would run MIPS at their clock rates as well. The question is how long it takes to get from start of program to finish of program. If the RPM40 is exeucting more loads and stores and more register to register moves to make up for the relatively small number of registers and lack of three-address instructions, etc., then you aren't getting all the bang out of your 40 MHz. On the other hand, if it *is perfect for your application* then great. >] If the latter, I think >] you are wrong. To be less opaque, I think that the RPM40 VAX-equivalent >] MIPS is no better than, say, a 25 MHz Am29000 or a 16 MHz MIPS (both >] with caches, you understand; and I am not saying that the 25 MHz 29000 is >] the same as a 16 MHz MIPS). We're talking integer here. > >I think YOUR wrong, and I am in a better position to say so. >Don't you think you're being a little quick with your evaluation ? >How much do you know about RPM40 ? This is where I don't appologize for saying something. I'll confine the following discussion to the Am29000 since I know it well: With similar very fast memories (as the RPM40 assumes), the Am29000 will have the advantage in fewer loads/stores, faster procedure calls, and fewer instructions executed (three-address instructions and lots of registers). The RPM40 has the advantage in clock rate. Who wins? I don't know, but I doubt the difference is tremendous, especially if the RPM40 is required to have a TLB as the Am29000 does. >Look, even I don't know how much real "VAX-equivalent" performance >this chip has, except that it has LOTS, so how can anyone else ? >If anyone knew, I'd know, either because I determined it or >because someone would tell me (hi Pete, hi Phil, if you're there :-) It isn't always necessary to know absolute numbers. But you are right, I certainly don't know the VAX-equivalent peformance. Architectural issues aside, the RPM40 must be evaluated with a TLB in order to be compared to most other chips. Incidentally, I think MIPS would rather have the R2000 known as a 10 MIPS machine at 16 MHz (not the 8 MIPS you quoted). The Am29000 is designed to work with more than one memory configuration, so its Vax MIPS at 25 MHz is not a single number. In your reponse to my response, you go on to say that we should not judge performance by either peak native instructions per second or MHz. I don't know anyone here who would dissagree with you (except marketing people: what else can they say?). In my claim above, I adhered to just that philosophy. This also is what most manufacturers of concern to us here strive for (esp. MIPS Co.).