Path: utzoo!utgpu!water!watmath!clyde!att-cb!att-ih!pacbell!ames!hc!lll-winken!lll-lcc!pyramid!voder!apple!bcase
From: bcase@Apple.COM (Brian Case)
Newsgroups: comp.arch
Subject: Re: Split IN and OUT Data Bus Tradeoffs
Message-ID: <7596@apple.Apple.Com>
Date: 8 Mar 88 18:58:32 GMT
References: <7538@apple.Apple.Com> <9825@steinmetz.steinmetz.UUCP>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc, Cupertino, CA
Lines: 7

An article by david@daisy.UUCP (David Schachter) says:
> Which leads to the question: if pin limitations were not a factor, would
> it be a Good Idea to split the data bus into two busses: IN and OUT?

Note that splitting I/O at the processor chip boundaryis only going to be
a win if the memory has separate I/O; otherwise, you'll still have to turn
a bus around somewhere.  Note that some of the fastest SRAMs from people
like Cypress and Performance have separate I/O.