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From: lindsay@K.GP.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Harvard Architecure
Message-ID: <1071@PT.CS.CMU.EDU>
Date: 9 Mar 88 05:22:24 GMT
References: <8803011911.AA06922@decwrl.dec.com> <3460011@hpsrla.HP.COM>
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Organization: Carnegie-Mellon University, CS/RI
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In article <3460011@hpsrla.HP.COM> brucek@hpsrla.HP.COM (Bruce Kleinman) 
 writes about the 68030:
>Ahh, those massive 256-Byte caches are really going to speed this puppy up :-)

Actually, it will. Remember, the CDC 6600 got a win from an "instruction
stack" of 480 bits ! 

Plus, the two caches access in parallel (versus the one cache of the 68020).
Plus, the caches now take one clock (versus 2 on the 68020).
Plus, the caches now have burst refill (if the board designer supports it,
of course.)

All in all, a clear improvement. I don't hear any suggestions as to a better
use for the silicon.
-- 
	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science