Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Yield of core-MIPS chips
Message-ID: <1806@obiwan.mips.COM>
Date: 8 Mar 88 17:20:29 GMT
Lines: 33
Keywords: Query

In article <9792@steinmetz.steinmetz.UUCP>, oconnor@sunset.steinmetz
(Dennis M. O'Connor) says:
	> {referring to GE RPM-40} It's currently running 40MIPS on
	> a wire-wrap board. We haven't said it won't or doesn't run
	> faster, 40MIPS is what it was designed to do, using
	> conservative design rules.

First, a remark.  The photograph shown at ISSCC was of a motherboard/
daughterboard configuration.  The daughterboard contains the RPM-40
CPU and a FP coprocessor socket, and it was a green epoxy _PC board_.
It hasn't been stated (yet) how many layers of PC traces exist on
that board, how many power/ground planes, or how many local bypass
capacitors was on it {around or ?in? the sockets} to make the CPU happy.
True enough, the motherboard into which the CPU's PC board plugged,
was wire wrapped.  Motherboard contained SRAM chips, a crystal, &c.


Second, a question.  The other DARPA core-MIPS paper at the ISSCC
(a 200-MIPS GaAs bipolar device from Texas Instruments) devoted a
segment of the oral presentation to chip yield.  They were quite
pleased to reveal their exact percentage yields to date (on this
DARPA-funded project) and to give their yield projections for the
next 12 months or so.

Could somebody from GE tell us what the yield is on the GE DARPA
core-MIPS chip?  TI's data included (a) # of core-MIPS chips built
to date; (b) # of them that are fully-functional, (c) trendline
predictions of (b)/(a) for the near future.

Thanx,
-- 
 -Mark Johnson	*** DISCLAIMER: Any opinions above are personal. ***	
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