Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!amdcad!phil
From: phil@amdcad.AMD.COM (Phil Ngai)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <20749@amdcad.AMD.COM>
Date: 10 Mar 88 04:00:18 GMT
References: <9792@steinmetz.steinmetz.UUCP> <9852@steinmetz.steinmetz.UUCP> <7613@apple.Apple.Com>
Reply-To: phil@amdcad.UUCP (Phil Ngai)
Organization: Advanced Micro Devices
Lines: 18

In article <7613@apple.Apple.Com> bcase@apple.UUCP (Brian Case) writes:
>In article <9852@steinmetz.steinmetz.UUCP> sungoddess!oconnor@steinmetz.UUCP writes:
<<What's the smallest signal interval on a 25MHz Am29000 ? In the RPM40,
<<NO signal ever assumes more than one valid state during a cycle.
<<This is not true of the R2000. Is it true of Am29000 ? 
<
<I'm not sure I understand exactly what you mean; but I think the smallest
<signal interval is one clock cycle (i.e., the channel is synchronized to

Brian, I believe you are correct in your understanding of Dennis'
question. Saying no signal ever assumes more than one valid state
during a cycle is the same as saying no signal makes more than one
transition per cycle. Except for the clock signal, this is true
for the 29000.
-- 
 300 Mb on a Sun-3/60 for $2,300, quantity 1!

I speak for myself, not the company.
Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or phil@amd.com