Path: utzoo!mnetor!uunet!steinmetz!sungoddess!oconnor From: oconnor@sungoddess.steinmetz (Dennis M. O'Connor) Newsgroups: comp.arch Subject: Re: RPM-40 microprocessor @ 40 MHz; dat Message-ID: <9875@steinmetz.steinmetz.UUCP> Date: 10 Mar 88 14:43:04 GMT References: <9852@steinmetz.steinmetz.UUCP> Sender: news@steinmetz.steinmetz.UUCP Reply-To: oconnor%sungod@steinmetz.UUCP Organization: GE Corporate R&D Center Lines: 71 Brian Case wrote a very good article. I understand that he is NOT trying to "slander" the RPM40. No problem. I haven't taken it that way. The only time, I think, I've gotten defensive was when John Mashey claimed the the RPM40 would NOT make a "good UNIX box". I don't beleive RPM40 would be the "best", or even a "better", UNIX box than a MIPS Inc. R2000, or an Am29000. I just objected to him saying it WOULD NOT make a good one. In reference to my VUPS-MIPS-MHz comment, please allow me to clarify : Although I do NOT think peak-native-MIPS is a good "marketing" figure, or a figure-of-merit. But that doesn't mean it isn't an important consideration in architecture. However, I'm not particularly sure why I feel it is important. Clock speed, in MHz, is an important factor. There's only so fast any particular technology can be pushed, so if two processors have the same performance, but one is using a 25MHz single-phase clock, while the other is using a 50MHz four-phase clock, well, which one do you think will eventually run faster ? But is this an architecture or an implementation question ? Seems to me the influence goes both ways across the architecture/implementation line. More inportant than "clock speed" is, of course, the width of the smallest valid state of any external signal. CMOS, anyway, has a HELL of a hard time driving external loads ( damn that 50pf load, anyway ), so a CMOS chip that puts "n" state changes on some external signal per cycle is gonna "hit the wall" before a 1-state-change-per-cycle ( which includes when the state change is out-of-phase ) chip. As Brian Case correctly points out, as transistor counts go up, that "external" signal with n-changes per cycle may become internal with the next design. This is true, but is a cop-out, I think. If the current chip has this property, it has it. No drop-in replacement for the current chip will ever be able to get around it. Of course, with today's nearly-disposable systems ( "You don't really want to keep all that SLOW 200ns RAM, anyway, so replace the whole system!" ), the "drop-in replacement" part may not be relevant anyway. After all making money mmay no be everything, but if you don't you'll go out of business. IBM knows this well. Do you think they care about technological leadership of released products ? Look, how about we not worry so much about getting our feelings hurt ( yeah, I ben guilty o 'dat me-self ) and just have a GOOD TIME discussing/debating architecture ? I'm not out to dump on anybody, I have no "chip" on my ... well now that you mention it I do kinda ... well anybody, I'd like to be able to discuss what is wrong with a particular design, or right, without people taking it personally. I try not too : you people don't even KNOW me ! Remeber, on the NET, no one will ever comment on what you say unless they think it's WRONG WRONG WRONG! :-) BTW, I read that someone's proved Fermat's last theorum. Well, actually, the proof's being checked now. -- Dennis O'Connor oconnor%sungod@steinmetz.UUCP ARPA: OCONNORDM@ge-crd.arpa ( I wish I could be civil all the time, like Eugene Miya ) (-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)