Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!amdahl!nsc!grenley
From: grenley@nsc.nsc.com (George Grenley)
Newsgroups: comp.arch
Subject: CPU chip cache sizes, was Re: Harvard Architecure
Message-ID: <5009@nsc.nsc.com>
Date: 11 Mar 88 20:29:41 GMT
References: <8803011911.AA06922@decwrl.dec.com> <3460011@hpsrla.HP.COM> <1071@PT.CS.CMU.EDU>
Reply-To: grenley@nsc.UUCP (George Grenley)
Organization: National Semiconductor, Sunnyvale
Lines: 27
Summary: bigger is better

In article <1071@PT.CS.CMU.EDU> lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) writes:
>In article <3460011@hpsrla.HP.COM> brucek@hpsrla.HP.COM (Bruce Kleinman) 
> writes about the 68030:
>>Ahh, those massive 256-Byte caches are really going to speed this puppy up :-)

I'm sure they will.  Heaven knows it needs it...


>Plus, the two caches access in parallel (versus the one cache of the 68020).

As do the two caches on the 32532

>Plus, the caches now take one clock (versus 2 on the 68020).

Likewise on the 532

>Plus, the caches now have burst refill (if the board designer supports it,
>of course.)

So does the 532.  We also have larger caches (512 instruction, 1K 2 way
set associative data).  I have seen the studies on hit rate vs size for
the 532; since the 030 is roughly similar architecture I expect they have
the same tradeoffs.  256 bytes is better than no bytes, but it is still
pretty small.


George Grenley
NSC