Path: utzoo!mnetor!uunet!husc6!psuvax1!gondor.cs.psu.edu!przemek
From: przemek@gondor.cs.psu.edu (Przemyslaw Klosowski)
Newsgroups: comp.arch
Subject: Re: RPM-40 microprocessor @ 40 MHz; dat
Message-ID: <3356@psuvax1.psu.edu>
Date: 11 Mar 88 20:10:54 GMT
References: <9792@steinmetz.steinmetz.UUCP> <9852@steinmetz.steinmetz.UUCP> <1820@gumby.mips.COM>
Sender: netnews@psuvax1.psu.edu
Reply-To: przemek@gondor.cs.psu.edu (Przemyslaw Klosowski)
Organization: Penn State University
Lines: 24

In article <1820@gumby.mips.COM> earl@mips.COM (Earl Killian) writes:
>In article <9852@steinmetz.steinmetz.UUCP> oconnor@sungoddess.steinmetz (Dennis M. O'Connor) writes:
>
>   Actually, I think MIPS Inc. actually claims a 10 Vax-MIPS rating for
>   their 16-native-peak-MIPS processor, that uses a 32MHz clock. Which
>   places addresses on the address bus once every 30ns. THAT's why
>The MHz figures are for cycle times, not the clock input.  We call the
>R2000 16.7MHz because its cycle time is 60.0ns.  The 2x frequency of
>the clock input is simply a convenience for generating two phase CMOS
>clocking.  Call it a 33.3MHz machine if you want, but that seems
>rather silly given that the phase clocks could theoretically be
>generated internally from a 1x clock input.

I strongly disagree. You could internally generate its clock from 1 Hz external
clock ;^) the performance issue is how fast are the signals in the chip running,
and what is on the I/O pins. To be (over)precise: what is the fundamental 
frequency in the inside and  on the edge of the chip.


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