Path: utzoo!mnetor!uunet!tektronix!reed!percival!littlei!omepd!news From: news@omepd (News Account) Newsgroups: comp.arch Subject: Re: Yield of core-MIPS chips [MIPSCo yield? && Other Issues] Message-ID: <2904@omepd> Date: 11 Mar 88 18:39:42 GMT References: <1806@obiwan.mips.COM> Reply-To: mcg@iwarpo3.UUCP (Steve McGeady) Organization: Intel Corp., Hillsboro Lines: 117 Keywords: Query -------- From: mcg@iwarpo3.intel.com (Steve McGeady) Path: iwarpo3!mcg In article <1806@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >Second, a question. The other DARPA core-MIPS paper at the ISSCC >(a 200-MIPS GaAs bipolar device from Texas Instruments) devoted a >segment of the oral presentation to chip yield. They were quite >pleased to reveal their exact percentage yields to date (on this >DARPA-funded project) and to give their yield projections for the >next 12 months or so. > >Could somebody from GE tell us what the yield is on the GE DARPA >core-MIPS chip? TI's data included (a) # of core-MIPS chips built >to date; (b) # of them that are fully-functional, (c) trendline >predictions of (b)/(a) for the near future. This opens a very interesting can of worms. I would like to ask MIPSCo what *their* chip yield is. And lest I be accused of pursuing a hidden agenda, here it is: This newsgroup (comp.arch) tends to focus on a very narrow band of issues concerning the success (intellectually and commercially) of architectures and their implementations. The predominant issues discussed here are performance, "capability", and architectural elegance. All too seldom do we discuss issues that, ultimately are more important to the success of an architecture: -> bug-free, working silicon -> yield (affects price, availability) -> system integration issues -> HW interface complexity -> availability of compatible interface chips -> support tools -> availability of compilers, tools -> development environment -> software support -> debug capabilities (ICE, SW debug, others) -> hardware support -> demonstration designs We've heard much (too much, some would say) from MIPSCo regarding the raw performance of their processor. I, for one, would be interested in hearing some other questions answered, for instance: 1) Who manufactures your silicon, on what process, what yield do you get, and how does/will this influence chip prices? [I suppose this begs the question of whether MIPSCo is primarily a chip, board, or system vendor - I have heard all three as the answer at various points in the last few years]. 2) Without a captive silicon manufacturing establishment, how can your silicon-foundry-provided 2-micron CMOS technology effectively compete with sub-micron technology from manufacturers with captive silicon development technology? 3) What is the availability of development tools (compilers, assemblers, debuggers) on VAXen, SUN's, and PC's? 4) What is the complexity of integrating a MIPSCo chip set into a system? What amount and kind of support HW is needed? As a more general question to this group, what does it take to make an architecture successful? It can't be elegance of design, for (e.g.) the 80386 and the MIPSco processor are each somewhat inelegant in their own ways (for those who don't wish to fill in the blanks, segmentation and register model in the former case, exposure of pipeline and other implementation details in the latter); It can't be raw speed, for slower processors (e.g. the 68020 and the 80386) are still consistently out-selling faster ones; It can't be ease of UNIX ports, because the original 68000 UNIX ports (e.g. Sun-1 and Apollo) were exercises in frustration (usually due to memory management limitations); And it certainly can't be volume of posting in comp.arch, or MIPSco would have gone public long since. My stab at an answer to this question: The answer is that there are many things that contribute, including marketing (both hype and non-hype), but (and forgive me if this sounds circular), what makes an architecture is VOLUME. An architecture is successful if you sell a lot of the chip implementing that architecture. This is because volume lowers the price of the part, encourages third parties to develop software for it, and in general increases familiarity with the architecture, lowering the learning curve for new designs and the "fear factor" many have. Put another way, I would much rather have designed a processor that found its way into every anti-skid braking system, microwave oven and laser-printer than to have designed a processor that was used only in a particular $100,000 software engineering workstation. I've rambled on long enough. Now, to Mr. Johnson's answer about MIPSCo yield - I'm very interested, and I thank him for giving me an excuse to raise the issue. S. McGeady Intel Corp. p.s. - If you counter with 'what is Intel's yield on (e.g.) the 386', I will have to answer that this is considered one of Intel's most proprietary pieces of information, and I couldn't reveal it even if I knew the answer, which I don't. I can say, however, that we shipped 1,000,000 386's in 1987, and expect to ship more than that in 1988, ugly architecture and all.