Path: utzoo!mnetor!uunet!mcvax!enea!tut!pv
From: pv@tut.fi (Vuorimaa Petri Kalevi)
Newsgroups: comp.arch
Subject: Re: Harvard Architecure
Message-ID: <2781@korppi.tut.fi>
Date: 12 Mar 88 14:39:02 GMT
References: <7614@apple.Apple.Com>
Organization: Tampere University of Technology, Finland
Lines: 25

From article <7614@apple.Apple.Com>, by bcase@Apple.COM (Brian Case):

> A little birdie with an EE degree told me that you can expect maybe a 20%
> improvement over a 68020 at the same clock rate.  An improvement, yes, but
> a better use of silicon might have been some on-chip floating point.

Floating point unit takes much more space than instruction cache.
Actually more room than memory management unit and instruction cache
together. You must also remember that there's just not that much
more space on the chip: Motorola had to drop the number of address
translation cache entries from 64 (MC68851) to 22 (MC68030) to fit MMU in.
At this moment it's just not possible to add on-chip floating point unit
to MC68020. So, Motorola made the best choice they could.

> Or how about more pins so as to expose the harvard architecture to the
> external world?

That means nearly 200 pins (128 + 32 + 32 + control signals).
And that's much more than I myself have ever seen (or is there such?).
If the address space for instructions was smaller, then maybe 
it could be possible, but that causes troubles for the applications
all ready using MC68020. 
-- 
Petri Vuorimaa	   Tampere University of Technology / Computer Systems Lab
pv@tut.FI          PO. BOX. 527, 33101 Tampere, Finland