Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!prls!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: CPU chip cache sizes, was Re: Harvard Architecure
Message-ID: <1853@winchester.mips.COM>
Date: 12 Mar 88 03:45:25 GMT
References: <8803011911.AA06922@decwrl.dec.com> <3460011@hpsrla.HP.COM> <1071@PT.CS.CMU.EDU> <5009@nsc.nsc.com>
Reply-To: mash@winchester.UUCP (John Mashey)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 19

In article <5009@nsc.nsc.com> grenley@nsc.UUCP (George Grenley) writes:
>So does the 532.  We also have larger caches (512 instruction, 1K 2 way
>set associative data).  I have seen the studies on hit rate vs size for
>the 532; since the 030 is roughly similar architecture I expect they have
>the same tradeoffs.  256 bytes is better than no bytes, but it is still
>pretty small.

I recall there was speculation when the 68030 was announced that the
D-cache might actually cost you performance in general applications,
and that people would end up turning it off [unlike the I-cache,
where even a small cache is almost always useful].  
However, I've seen no data published one way or another on this yet,
and I don't have any.
Do you (or anybody else) have any good data on a 256-byte cache with
16 16-byte lines? (i.e., the 68030 D-cache)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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