Path: utzoo!mnetor!uunet!husc6!cmcl2!nrl-cmf!ames!elroy!cit-vax!ucla-cs!oahu!marc
From: marc@oahu.cs.ucla.edu (Marc Tremblay)
Newsgroups: comp.arch
Subject: Re: 16 & 32 bit vs 32 bit only instructions for RISC.
Message-ID: <10369@shemp.CS.UCLA.EDU>
Date: 15 Mar 88 16:47:50 GMT
References: <9651@steinmetz.steinmetz.UUCP> <9678@steinmetz.steinmetz.UUCP> <15580@onfcanim.UUCP> <12705@sgi.SGI.COM>
Sender: news@CS.UCLA.EDU
Reply-To: marc@oahu.UUCP (Marc Tremblay)
Organization: UCLA Computer Science Department
Lines: 40

In article <12705@sgi.SGI.COM> bron@olympus.SGI.COM (Bron C. Nelson) writes:
>
>Several respondents have said "its expensive" or "it takes more time
>to decode the different formats"  and even "fetching the registers in
>parallel with doing the instruction decode is a big win."  (None of
>these are probably exact quotes.)  I sorta wonder at this.  Is the
>instruction decode/register fetch a critical path?   From what I
>can gather, the register fetch probably IS.  

The processor that we are designing here at UCLA has a large register
file (64 locals + 10 globals) with overlapping windows. Because of 
fault tolerance aspect of the chip, we have to decode the full 
address (7 bits) of the register operands everytime an access is made
to the register file. The window pointer can not be pre-decoded.
This means that our critical path is composed of a fairly long decode
and of a quite long register fetch. It turned out that using an
efficient decoder (dedicating some extra area), the decode part
represents about 12% of the critical path.
The fact is that using a simple instruction encoding we are able
to overlap the register decoding/fetching with the instruction
decoding done by a separate unit. Adding complexity in the register
address decoding would affect the critical path directly.

>p.s.  If we only have 2 formats, we can specify which one by using the
>first bit in the instruction (much like CRISP uses the first bit(s)).

I assume that this "first" bit is available for encoding... 

>This should (?) let us select between the 2 possible register
>encodings with only a single additional gate delay (and some more
>silicon devoted to doing it).  

Using a tighter encoding, the time spent decoding the rest of the 
instruction (opcode) may turn out to shift the critical path to 
the control unit instead of the register file.

					Marc Tremblay
					marc@CS.UCLA.EDU
					...!(ihnp4,ucbvax)!ucla-cs!marc
					Computer Science Department, UCLA