Path: utzoo!mnetor!uunet!husc6!mailrus!nrl-cmf!ames!hc!lll-winken!lll-lcc!pyramid!prls!mips!hansen
From: hansen@mips.COM (Craig Hansen)
Newsgroups: comp.arch
Subject: Re: Yield of core-MIPS chips [MIPSCo yield? && Other Issues]
Message-ID: <1869@mips.mips.COM>
Date: 15 Mar 88 17:10:21 GMT
References: <1806@obiwan.mips.COM> <2904@omepd> <10355@shemp.CS.UCLA.EDU>
Lines: 62
Keywords: Query

In article <10355@shemp.CS.UCLA.EDU>, marc@oahu.cs.ucla.edu (Marc Tremblay) writes:
> In article <2904@omepd> mcg@iwarpo3.UUCP (Steve McGeady) writes:
> >We've heard much (too much, some would say) from MIPSCo regarding the
> >raw performance of their processor.  I, for one, would be interested in
> >hearing some other questions answered, for instance:
> >	1) Who manufactures your silicon, on what process, what yield
> >	   do you get, and how does/will this influence chip prices?
> As far as I know MIPSCo has agreements with three companies to 
> manufacture and sell their processor. Each of the companies has
> rights to both the 12.5 MHz and 16.7 MHz version.
> The three companies are:
> 	i)   LSI Logic Corp 
> 	ii)  Integrated Device Technology Inc.
> 	iii) Performance Semiconductor Corp.

These companies also have rights to future, higher-performance designs.

> >	2) Without a captive silicon manufacturing establishment, how
> >	   can your silicon-foundry-provided 2-micron CMOS technology
> >	   effectively compete with sub-micron technology from
> >	   manufacturers with captive silicon development technology?
> Performance Semiconductor Corp. has a high-speed CMOS process
> using submicron technology.

All three companies have competitive CMOS technology.

> >	4) What is the complexity of integrating a MIPSCo chip set
> >	   into a system?  What amount and kind of support HW is needed?
> I would also like to know more about that one. (MIPS guys?)

For all the belly-aching about multiplexed busses and multiphase
clocks, integrating a MIPS chip set is easier than most
microprocessors, particularly when you consider that a
_high-performance_ micro needs to have external cache hand-crafted by
the system designer, whereas on the MIPS chip, the cache is formed
from some latches and buffers and off-the-shelf, standard static
RAM's, available in quantity from multiple vendors. All the customised
hardware to use the SRAMs as caches are on the chip. [The SPARC chip
set also requires a hand-crafted MMU design; we have the MMU on chip.]
The support HW required is:

	1) a 2x frequency oscillator
	2) a tapped delay line
	3) some '373 latches
	4) some 1804 buffers
	5) some fast SRAM

The number of latches, buffers, and SRAM depends on the size of
the caches you choose; anything from 4kb to 64kb for each of the
instruction and data caches is permitted in the current parts.
This can all be hooked up in cookbook fashion; we provide design data
that shows how it all goes together. Because of the processor's high
speed, and its write-through caches, writes to memory occur rather
frequently, so we also provide a set of gate arrays that form a 4-deep
FIFO between the fast processor and a slower main memory system.
The use of these gate arrays is optional, but they're easy to use
and improve performance about 10% over having a one-deep write buffer.

-- 
Craig Hansen
Manager, Architecture Development
MIPS Computer Systems, Inc.
...{ames,decwrl,prls}!mips!hansen or hansen@mips.com   408-991-0234