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From: suneel@hpclskj.HP.COM (Suneel Jain x75763)
Newsgroups: comp.arch
Subject: Re: Instruction Scheduling
Message-ID: <650001@hpclskj.HP.COM>
Date: 17 Mar 88 02:05:09 GMT
References: <12513@sgi.SGI.COM>
Organization: HP ITG/ISD Computer Language Lab
Lines: 25

> From: firth@sei.cmu.edu (Robert Firth)

> Thanks to Randell Jesup, Bron Nelson, and others for prompting
> this.  The question they discuss is, how might one do some
> really good code reorganising for a machine with pipeline
> constraints, eg a RISC machine.

The Instruction Scheduler for the HP Precision Architecture uses 
aliasing information to determine if two memory references could
interfere with each other. This allows the scheduler to rearrange
loads and stores much better than if worst case assumptions are 
used. This has been especially useful in scheduling floating 
point operations.

The aliasing information is computed by the various front ends and
passed down to the level where the scheduler is run. This process is
described in the following paper:

    Deborah S. Coutant, "Retargetable High-Level Alias Analysis",
    Proc. ACM Symposium on Principles of Programming Languages, 
    January 1986, pp 110-118. 

Suneel Jain
Hewlett-Packard
suneel@hpda.HP.COM