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Path: utzoo!mnetor!uunet!husc6!tut.cis.ohio-state.edu!mailrus!ames!sgi!bron
From: bron@olympus.SGI.COM (Bron C. Nelson)
Newsgroups: comp.misc,comp.arch
Subject: Instruction Scheduling
Message-ID: <12513@sgi.SGI.COM>
Date: 10 Mar 88 17:19:45 GMT
Sender: daemon@sgi.SGI.COM
Organization: Silicon Graphics Inc, Mountain View, CA
Lines: 27
Keywords: optimization   pipeline constraints  code re-organization


Recently jesup suggested we start talking about something else
and proposed reorganization algorithms as a topic.  I think this
is a fine idea.  Instruction scheduling/reorganization is a neat
field that still has lots of room for good ideas.  Also, it
is destined to become an increasingly "hot" topic as memory
latencies increase and asynchronous funtional units become more
and more common even in the micro world (the MIPS R2000 for example
has autonomous integer multiply and divide hardware that can
run overlapped with other "standard" ALU ops, and of course the
floating point co-processor runs autonomously as well).

This isn't really an architectural issue, so probably doesn't
really belong in comp.arch.  However, it does have interesting
architectural impact.  (For example, a machine similar to the
Multiflow VLIW (tm I think) machine could probably have been
BUILT years ago, but without something like a trace-scheduler,
the machine would be worthless.)  Also, there doesn't really
seem to be a good place to discuss this except perhaps comp.misc
(or comp.compilers, but I'd rather avoid moderation :-) at least
to start).  Ergo, I will post my first few articles on
this topic to comp.misc, cross-posted to comp.arch.  If enough
comp.arch people complain, I'll cease cross-posting.

Bron Nelson  bron@sgi.com
Silicon Graphics Inc.
Don't blame my employers for my opinions