Path: utzoo!mnetor!uunet!mcvax!ukc!strath-cs!jim From: jim@cs.strath.ac.uk (Jim Reid) Newsgroups: comp.sys.hp Subject: Re: hp9000 ser. 500 hpux Message-ID: <881@stracs.cs.strath.ac.uk> Date: 16 Mar 88 11:41:52 GMT References: <987@maccs.UUCP> <4760006@hpfcls.HP.COM> <672@kuling.UUCP> Reply-To: jim@cs.strath.ac.uk Organization: Comp. Sci. Dept., Strathclyde Univ., Scotland. Lines: 21 In article <672@kuling.UUCP> irf@kuling.UUCP (Bo Thide) writes: >............. So the logical question here is: Why doesn't HP have a >multi-CPU 800? Was the experience with the 500 series so bad that HP has >given up that idea? No, it's probably because building closely-coupled multiprocessors that use RISC (eg the 800 series CPU) isn't easy. RISC architectures like to have on-chip caches, N-deep pipelines and all sorts of things like that. This causes horrendous problems when you try to keep the value of shared variables (eg kernel data structures) consistent. eg CPU #X updates some variable, while CPU #Y still has an old copy in its cache and CPU #Z is just about to fetch an even older copy from its register file. Jim -- ARPA: jim%cs.strath.ac.uk@ucl-cs.arpa, jim@cs.strath.ac.uk UUCP: jim@strath-cs.uucp, ...!uunet!mcvax!ukc!strath-cs!jim JANET: jim@uk.ac.strath.cs "JANET domain ordering is swapped around so's there'd be some use for rev(1)!"