Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!ucsd!sdcsvax!ucsdhub!hp-sdd!hplabs!hp-pcd!hpcvca!scott
From: scott@hpcvca.HP.COM (Scott Linn)
Newsgroups: comp.sys.ibm.pc
Subject: Re: caution when cranking up the CPU clock
Message-ID: <4490007@hpcvca.HP.COM>
Date: 4 Mar 88 17:53:04 GMT
References: <49@vsi.UUCP>
Organization: Hewlett-Packard Co., Corvallis, Oregon
Lines: 16


In NMOS technology, power is *not* totally independent of clock rate.
There are two sinks where power goes: DC and AC.  The DC power is
dissipated when an inverter/nand/etc gate is driving low; the pullup
to Vdd is a simple resistor which dissipates power when the other side
is pulled to ground.  The AC power is equal to C(Vdd^2)f, where C is
the capacitive load, Vdd is 5V, and f is the toggling frequency of the
driven node.  If you have 16 drivers on the output bus driving 100 pf at
4 Mhz, you get .16W.  Of course, if the DC power is 5W it's no big deal,
but it does make a difference.

The time where Vdd is shorted to GND does not always happen; the amount
of "crowbar" current depends on the design.  We always try to eliminate
this current, and thus have just the C(Vdd^2)f power dissipation.

Scott Linn
HP - Northwest IC Division