Path: utzoo!utgpu!water!watmath!clyde!att-cb!att-ih!pacbell!amdahl!nsc!misha
From: misha@nsc.nsc.com (Michael Umansky)
Newsgroups: comp.sys.ibm.pc
Subject: DRAM speed vs CPU/BUS speed
Message-ID: <5003@nsc.nsc.com>
Date: 8 Mar 88 01:55:55 GMT
Organization: National Semiconductor, Sunnyvale
Lines: 15

I am not sure if this has been discussed before but ...

Does anyone know the relationship between DRAM access time and CPU/BUS speed
in following combinations, I think I want to know the wait states needed:

CPU/BUS		DRAM ACCESS TIME
SPEED
		150ns	120ns	100ns	 80ns
 5 Mhz		  ?	  ?	  ?	  ?
 6 Mhz		  ?	  ?	  ?	  ?
 8 Mhz		  ?	  ?	  ?	  ?
10 Mhz		  ?	  ?	  ?	  ?
12 Mhz		  ?	  ?	  ?	  ?
16 Mhz		  ?	  ?	  ?	  ?
20 Mhz		  ?	  ?	  ?	  ?