Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!elroy!cit-vax!cit-vlsi!flaig From: flaig@cit-vlsi.Caltech.Edu (Charles M. Flaig) Newsgroups: sci.electronics Subject: Re: Help with L measurement Message-ID: <5820@cit-vax.Caltech.Edu> Date: 16 Mar 88 23:01:18 GMT References: <1872@mips.mips.COM> Sender: news@cit-vax.Caltech.Edu Reply-To: flaig@cit-vlsi.UUCP (Charles M. Flaig) Organization: California Institute of Technology Lines: 33 Keywords: inductance of chip ground In article <1872@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: > >I have a problem. I'm trying to measure the inductance of a >gate-array (IC pin + package trace + bondwire), i.e. the total >inductance between the ground plane of my printed circuit board and >the on-chip ground metallization inside my gate-array IC. [explains he tried ringing a tank circuit, didn't work] Well, you could try to find the delay of an LC circuit (if you have a fast enough rise/fall time for your input waveform): -------- -------------- Square |_____________| Package |____________ Delayed waveform Wave | | | Inductance | | -------- | -------------- | | 10-30nH __|__ | _____ 100pf + Cscope V | Original __|__ waveform / / / After subtracting out the RC delay you should be left with the LC delay, and be able to calculate L. If necessary, you could put several package and capacitor stages in series for longer delays but messier calculations. I don't remember what the formula for LC delay is, but any electromagnetics text should have it. ______________________________________________________________________________ ___ , , ,;,;;;, / Y /| /| Charles Flaig ;/@-@\; | |/ __, ,__ |/ flaig@csvax.caltech.edu | ^ | | /^\ / | | | / /\ /\ \=/ \____/| \_/|_/\_/ \_/ \_\/_/_/_/ "What, you think they PAY me for this?"