Path: utzoo!mnetor!uunet!husc6!tut.cis.ohio-state.edu!osu-cis!att-cb!att-ih!ihnp4!inuxc!iuvax!pur-ee!uiucdcs!uiucdcsm!grunwald
From: grunwald@uiucdcsm.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: Instruction Scheduling
Message-ID: <3300024@uiucdcsm>
Date: 16 Mar 88 21:37:00 GMT
References: <12513@sgi.SGI.COM>
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Nf-ID: #R:sgi.SGI.COM:12513:uiucdcsm:3300024:000:844
Nf-From: uiucdcsm.cs.uiuc.edu!grunwald    Mar 16 15:37:00 1988


The paper by Wall keeps the Front-end/Back-end strategy, it just moves
the point of actual code generation to a later phase of the binding.
The linkers all use the IR generated by the front end. The last stage
is a translation of the linked IR to the machine code. 

The last stage (IR -> Assembler) performs global register allocation. The
advantages are that you have better information about other subroutines
at link time, and you can pass subroutine parameters in registers.

If you look at the improvements listed in tables 2, 4 and 5, you see that
the run-time information contibutes about as much improvement as
register coloring, but the two combined rarely perform significantly better
than one or the other.

This leads one to question the advantages of
	(1) Doing both
	(2) Bothering with recording the run-time data

Any comments?