Path: utzoo!mnetor!uunet!husc6!ukma!uflorida!codas!pdn!alan
From: alan@pdn.UUCP (Alan Lovejoy)
Newsgroups: comp.arch
Subject: Re: Harvard Architecure
Message-ID: <2594@pdn.UUCP>
Date: 18 Mar 88 22:02:40 GMT
References: <8803011911.AA06922@decwrl.dec.com> <3460011@hpsrla.HP.COM> <1071@PT.CS.CMU.EDU> <7614@apple.Apple.Com>
Reply-To: alan@pdn.UUCP (0000-Alan Lovejoy)
Organization: Paradyne Corporation, Largo, Florida
Lines: 29

In article <7614@apple.Apple.Com> bcase@apple.UUCP (Brian Case) writes:
/In article <1071@PT.CS.CMU.EDU> lindsay@K.GP.CS.CMU.EDU (Donald Lindsay) writes:
/>In article <3460011@hpsrla.HP.COM> brucek@hpsrla.HP.COM (Bruce Kleinman) 
/> writes about the 68030:
/>>Ahh, those massive 256-Byte caches are really going to speed this puppy up :-)
/
/Talking about 68030.
/
/>
/>Actually, it will. Remember, the CDC 6600 got a win from an "instruction
/>stack" of 480 bits ! 
/>
/>All in all, a clear improvement. I don't hear any suggestions as to a better
/>use for the silicon.
/
/A little birdie with an EE degree told me that you can expect maybe a 20%
/improvement over a 68020 at the same clock rate.  An improvement, yes, but
/a better use of silicon might have been some on-chip floating point.  Or
/how about more pins so as to expose the harvard architecture to the external
/world?

The 68020 **CONSISTENTLY** benchmarks twice as fast with the instruction
cache turned on (compared to its being turned off).  Apparently the
'030 gets **AT LEAST** a 30% performance boost from turning on the data
cache (so I have been told by those who have benchmarked one).

Enough said.

--alan@pdn