Path: utzoo!mnetor!uunet!husc6!tut.cis.ohio-state.edu!osu-cis!att-cb!att-ih!alberta!calgary!radford
From: radford@calgary.UUCP (Radford Neal)
Newsgroups: comp.arch
Subject: Re: Harvard Architecure (really 680x0 caches)
Message-ID: <1475@vaxb.calgary.UUCP>
Date: 20 Mar 88 19:24:49 GMT
References: <8803011911.AA06922@decwrl.dec.com> <3460011@hpsrla.HP.COM> <2594@pdn.UUCP>
Organization: U. of Calgary, Calgary, Ab.
Lines: 25

In article <2594@pdn.UUCP>, alan@pdn.UUCP (Alan Lovejoy) writes:

> The 68020 **CONSISTENTLY** benchmarks twice as fast with the instruction
> cache turned on (compared to its being turned off).  Apparently the
> '030 gets **AT LEAST** a 30% performance boost from turning on the data
> cache (so I have been told by those who have benchmarked one).
> 
> Enough said.

This is a bit hard to believe, seeing as the 68020 takes two cycles
to access a word from cache, and only three to access the same word
from external memory (if my memory serves me right). Of course, the
external memory might be slow, and require wait states to be added
to the three cycles. If you're willing to go for that, however, I'm 
sure I could build a system in which turning on the cache speeds 
things up by a factor of ten. (Well, actually, I'm not sure I could,
not having much experience with a soldering iron, but you know 
what I mean... :-)

What's needed are data on: (1) the benefit of the '030's data
cache assuming zero wait states (and a 32-bit bus), (2) the
benefit for various other memory configurations, (3) the overall
benefit in systems typical of various applications.

    Radford Neal